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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75036
4 BIT SINGLE-CHIP MICROCOMPUTER
The PD75036 is a 75X series 4-bit single-chip microcomputer. The PD75036 is an expanded version of the PD75028. It has ROM and RAM with a larger capacity. The minimum instruction execution time of the PD75036 is 0.95 s. In addition to this high-speed capability, it contains an A/D converter and furnishes high-performance functions such as the serial bus interface (SBI) function that follows the NEC standard format, providing powerful features and high cost performance. A built-in PROM product, PD75P036, is also available. The PD75P036 is suitable for small-scale production or experimental production in system development. The following user's manual describes the details of functions. Be sure to read it before design.
PD75028 User's Manual: IEU-694
FEATURES
* Variable instruction execution time advantageous to high-speed operation and power-saving:
* 0.95 s, 1.91 s, or 15.3 s (at 4.19 MHz when the main system selected) * 122 s (at 32.768 kHz when the subsystem clock selected)
* * * *
Program memory (ROM) capacity: 16256 x 8 bits Data memory (RAM) capacity: 1024 x 4 bits Built-in A/D converter (8-bit resolution, successive approximation): 8 channels Powerful timer function: 4 channels * Usable for 16-bit integral A/D conversion and PWM output
* Built-in NEC standard serial bus interface (SBI) * Very low-power clock operation allowed (5 A TYP. at 3 V)
APPLICATIONS
Electric household appliances, air cooling/heating apparatus, cameras, and electronic measuring instruments
ORDERING INFORMATION
Part number Package 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP ( 14 mm) Quality grade Standard Standard
PD75036CW-xxx PD75036GC-xxx-AB8
Remark xxx is a mask ROM code number.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice. Document No. IC-3115 (O.D. No. IC-8611) Date Published October 1993 P Printed in Japan The mark 5 shows major revised points.
(c) NEC Corporation 1993
PD75036
FUNCTIONS
Item Instruction execution time Function * 0.95, 1.91, 15.3 s (Main system clock : 4.19 MHz operation) * 122 s (Subsystem clock : 32.768 kHz operation) 16256 x 8 bits 1024 x 4 bits * 4-bit manipulation : 8 * 8-bit manipulation : 4 48 12 24 12 CMOS input pins CMOS I/O pins N-ch open-drain I/O pins * On-chip pull-up resistor by software : 27 * On-chip pull-down resistor by software: 4 * Direct LED driving: 4 * Withstand voltage is 10 V * On-chip pull-up resistor by mask option * Direct LED driving: 4
On-chip memory
ROM RAM
General register
I/O port
Timer 4 channels Serial interface Bit sequential buffer Clock output A/D converter Vectored interrupt Test input System clock oscillator Standby function
* Timer/event counter * Basic interval timer : Can be used as watchdog timer * Clock timer : Buzzer output enabled Multifunction timer : Can be used as timer, free-running timer or counter for integration A/D converter, or for PWM output
* Three-wire serial I/O mode * Two-wire serial I/O mode * SBI mode 16 bits , fX/23, fX/24 , fX/26 (Main system clock: 4.19 MHz operation) * 8-bit resolution x 8 channels (successive-approximation) * Capable of low-voltage operation: VDD = 2.7 to 6.0 V External : 3, Internal : 4 External : 1, Internal : 1 * Ceramic/crystal oscillator for main system clock oscillation * Crystal oscillator for subsystem clock oscillation STOP/HALT mode -40 to +85 C 2.7 to 6.0 V * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP ( 14 mm)
5 5
Operating temperature range Operating voltage Package
2
PD75036
CONTENTS
1. 2. 3.
PIN CONFIGURATIONS (TOP VIEW) ....................................................................................... BLOCK DIAGRAM ...................................................................................................................... PIN FUNCTIONS .......................................................................................................................
3.1 3.2 3.3 3.4 3.5 PORT PINS ..................................................................................................................................... NON-PORT PINS ........................................................................................................................... PIN INPUT/OUTPUT CIRCUITS .................................................................................................. MASK OPTION SELECTION ....................................................................................................... CONNECTION OF UNUSED PINS ................................................................................................
4 6 7
7 9 11 13 14
4. 5.
ARCHITECTURE AND MEMORY MAP OF THE PD75036 .................................................. PERIPHERAL HARDWARE FUNCTIONS ................................................................................
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 PORTS ............................................................................................................................................. CLOCK GENERATOR .................................................................................................................... CLOCK OUTPUT CIRCUIT ............................................................................................................ BASIC INTERVAL TIMER .............................................................................................................. CLOCK TIMER ................................................................................................................................ TIMER/EVENT COUNTER .............................................................................................................. SERIAL INTERFACE ...................................................................................................................... A/D CONVERTER .......................................................................................................................... MULTIFUNCTION TIMER (MFT) ....................................................................................................
15 17
17 17 19 20 21 22 24 26 27
6. 7. 8. 9.
INTERRUPT FUNCTION ............................................................................................................ STANDBY FUNCTION ................................................................................................................ RESET FUNCTION ..................................................................................................................... INSTRUCTION SET ...................................................................................................................
29 31 31 32 39 52 54 55
10. ELECTRICAL CHARACTERISTICS .......................................................................................... 11. PACKAGE DIMENSIONS ........................................................................................................... APPENDIX A APPENDIX B DEVELOPMENT TOOLS ........................................................................................ RELATED DOCUMENTS ........................................................................................
3
PD75036
1. PIN CONFIGURATIONS (TOP VIEW)
* 64-pin plastic shrink DIP
SB1/SI/P03 SB0/SO/P02 SCK/P01 INT4/P00 BUZ/P23 PCL/P22 PPO/P21 PTO0/P20 MAT/P103 MAZ/P102 MAI/P101 MAR/P100 RESET X1 X2 IC XT1 XT2 VDD AVDD AVREF+ AVREF- AN7 AN6 AN5 AN4 AN3/P113 AN2/P112 AN1/P111 AN0/P110 AVSS TI0/P13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VSS P30 P31 P32 P33 P40 P41 P42 P43 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 P81 P82 P83 P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2
PD75036CW-xxx
* 64-pin plastic QFP
P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 P81 P82 P83
64 63 62 6160 59 58 57 56 55 54 53 52 51 50 4948 1 47 2 46 3 45 4 44 5 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 313233
P43 P42 P41 P40 P33 P32 P31 P30 VSS SB1/SI/P03 SB0/SO/P02 SCK/P01 INT4/P00 BUZ/P23 PCL/P22 PPO/P21
P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2 TI0/P13 AVSS AN0/P110 AN1/P111 AN2/P112 AN3/P113 AN4 AN5 AN6
IC: Internally connected (Should be directly connected to VDD)
4
PTO0/P20 MAT/P103 MAZ/P102 MAI/P101 MAR/P100 RESET X1 X2 IC XT1 XT2 VDD AVDD AVREF+ AVREF- AN7
PD75036GC-xxx-AB8
PD75036
Pin names P00-03 P10-13 P20-23 P30-33 P40-43 P50-53 P60-63 P70-73 P80-83 P90-93 : : : : : : : : : : Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Key Return Serial Clock Serial Input Serial Output Serial Bus 0, 1 Reset Input Timer Input 0 Programmable Timer Output 0 Buzzer Clock Programmable Clock External Vectored Interrupt 0, 1, 4 External Test Input 2 Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 Integration Control Autozero Control External Comparate Timing Input Programmable Pulse Output ... MFT timer mode AN0-7 AVREF+ AVREFAVDD AVSS VDD VSS : : : : : : : Analog Input 0-7 Analog Reference (+) Analog Reference (-) Analog VDD Analog VSS Positive Power Supply Ground : Pulse output ... MFT timer mode : Analog input : Analog reference voltage (+) input : Analog reference voltage (-) input : A/D converter power supply input : A/D converter GND input : Main power supply pin : GND potential pin : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 : Port 6 : Port 7 : Port 8 : Port 9 : Port 10 : Port 11 : Key interrupt input : Serial clock I/0 : Serial data input : Serial data output : Serial bus I/O : Reset input : External event pulse input : Timer/event counter output : Arbitrary frequency output : Clock output : External vectored interrupt input : External test input : Main system clock oscillation pin : Subsystem clock oscillation pin MFT A/D : Integration signal output : Autozero signal output mode : External comparator signal input
P100-103: P110-113: KR0-7 SCK SI SO SB0, 1 TI0 PTO0 BUZ PCL INT2 X1, 2 XT1, 2 MAR MAI MAZ MAT PPO : : : : : : : : : : : : : : : : :
RESET :
INT0, 1, 4:
Remark MFT: Multifunction timer

Reference Integration Control
: Reverse integration signal output
MFT A/D mode
5
2. BLOCK DIAGRAM
6
Basic interval timer INTBT Port 0 TI0/P13 PTO0/P20 Timer/ counter 0 INTT0 SI/SB1/P03 SO/SB0/P02 SCK/P01 INTCS1 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0-KR3/P60-P63 KR4-KR7/P70-P73 BUZ/P23 Watch timer INTW AVDD AVREF+ AVREF- AVSS AN0-AN3/P110-P113 AN4-AN7 MAR/P100 MAI/P101 MAZ/P102 MAT/P103 PPO/P21 PCL/P22 INTMFT XT1 XT2 X1 X2 VDD VSS RESET Multi function timer A/D converter Port 8 P80-P83 Interrupt control ROM program memory 16256 x 8 bits Port 5 Decode and control P50-P53 General register Port 4 P40-P43 Port 3 P30-P33 Serial interface Bank Port 2 P20-P23 Program counter ALU SP CY Port 1 P10-P13 P00-P03 Bit sequential buffer RAM data memory 1024 x 4 bits Port 6 P60-P63 Port 7 P70-P73 fX/2N Clock output control Clock generator Sub Main CPU clock Stand by control Port 9 P90-P93 Clock divider Port 10 P100-P103 Port 11 P110-P113
PD75036
PD75036
3. PIN FUNCTIONS
3.1 PORT PINS (1/2)
Pin P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30Note 2 P31Note 2 P32Note 2 P33Note 2 P40 - P43 Note 2 I/O I/O I/O Input/ output Input I/O I/O I/O Input Shared pin INT4 SCK SO/SB0 SI/SB1 INT0 INT1 INT2 TI0 PTO0 PPO PCL BUZ - - - - - N-ch open-drain 4-bit I/O port (PORT4). A pull-up resistor can be provided for each bit (mask option). This opendrain port has a withstand voltage of 10 V. High level (when pullup resistors are provided) or high impedance High level (when pullup resistors are provided) or high impedance M Programmable 4-bit I/O port (PORT3). I/O can be specified bit by bit. Pull-up resistors can be provided by software in units of 4 bits. x Input E-B 4-bit I/O port (PORT2). Pull-up resistors can be provided by software in units of 4 bits. x Input E-B With noise elimination function 4-bit input port (PORT1). Pull-up resistors can be provided by software in units of 4 bits. x Input Function 4-bit input port (PORT0). For P01 - P03, pull-up resistors can be provided by software in units of 3 bits. 8-bit I/O x When reset Input I/O circuit typeNote 1
B FF-A FF-B
M F-C
BF-C
P50 - P53 Note 2
I/O
-
N-ch open-drain 4-bit I/O port (PORT5). A pull-up resistor can be provided for each bit (mask option). This open-drain port has a withstand voltage of 10 V.
M
Notes 1. The circle (
) indicates the Schmitt trigger input.
2. Can directly drive the LED.
7
PD75036
3.1 PORT PINS (2/2)
Input/ output I/O Shared pin KR0 KR1 KR2 KR3 I/O KR4 KR5 KR6 KR7 I/O - 4-bit I/O port (PORT8). Pull-up resistors can be provided by software in units of 4 bits. 4-bit I/O port (PORT9). Pull-down resistors can be provided by software in units of 4 bits. N-ch open-drain 4-bit I/O port (PORT10). A pull-up resistor can be provided bit by bit (mask option). This open-drain port has a withstand voltage of 10 V. x x Input E-B 4-bit I/O port (PORT7). Pull-up resistors can be provided by software in units of 4 bits. Input
F F-A
Pin P60 P61 P62 P63 P70 P71 P72 P73 P80-P83
Function Programmable 4-bit I/O port (PORT6). I/O can be specified bit by bit. Pull-up resistors can be provided by software in units of 4 bits.
8-bit I/O
When reset Input
I/O circuit typeNote 1
F F-A
P90-P93
I/O
-
Input
E-D
P100Note 2 P101Note 2 P102Note 2 P103Note 2
I/O
MAR MAI MAZ MAT
High level (when pull-up resistors are provided) or high impedance Input
M
P110 P111 P112 P113
Input
AN0 AN1 AN2 AN3
4-bit input port (PORT11)
Y-A
Notes 1. The circle (
) indicates the Schmitt trigger input.
2. Can directly drive the LED.
8
PD75036
3.2 NON-PORT PINS (1/2)
Pin TI0 Input/ output Input Shared pin P13 Function Input for receiving external event pulse signal for timer/event counter Timer/event counter output Clock output Output for arbitrary frequency output (for buzzer output or system clock trimming) Serial clock I/O Serial data output Serial bus I/O Serial data input Serial bus I/O Edge detection vectored interrupt input (either rising edge or falling edge detection) Edge detection vectored interrupt input (detection edge selectable) Edge detection testable input (rising edge detection) Parallel falling edge detection testable input Parallel falling edge detection testable input In MFT integral A/D converter mode Reverse integration signal output Integration signal output Autozero signal output Comparator input In MFT timer mode Timer pulse output
Note 2 Note 3 Note 3
When reset -
I/O circuit typeNote 1
BF-C
PTO0 PCL BUZ
I/O I/O I/O
P20 P22 P23
Input Input Input
E-B E-B E-B
SCK SO/SB0
I/O I/O
P01 P02
Input Input
FF-A
FF-B
SI/SB1
I/O
P03
Input
M F-C
INT4
Input
P00
-
B
INT0 INT1 INT2
Input
P10 P11
-
BF-C
Input
P12
-
BF-C
KR0 - KR3 KR4-KR7 MAR MAI MAZ MAT PPO AN0 - AN3 AN4 - AN7 AVREF+
I/O I/O I/O I/O I/O I/O I/O Input
P60 - P63 P70 - P73 P100 P101 P102 P103 P21
Input Input
Note 4 Note 4 Note 4 Note 4
FF-A FF-A
M M M M E-B Y-A Y
Input Input
Input
P110 - P113 For A /D converter - only -
8-bit analog input
Reference voltage input (on AVDD side) Reference voltage input (on AVSS side) Operating power supply Reference GND potential
-
Z-A
AVREF-
Input
-
- - -
Z-A - -
AVDD AVSS
- -
- -
Notes 1. The circle ( 3. Asynchronous
) indicates the Schmitt trigger input.
2. Clock synchronous 4. High level (when pull-up resistors are provided) or high impedance Remark MFT: Multifunction Timer
9
PD75036
3.2 NON-PORT PINS (2/2)
Pin X1, X2 Input/ output Input Shared pin - Function Crystal/ceramic connection for main system clock generation. When external clock signal is used, it is applied to X1, and its reverse phase signal is applied to X2. Crystal connection for subsystem clock generation. When external clock signal is used, it is applied to XT1, and its reverse phase signal is applied to XT2, XT1 can be used as a 1-bit input (test). System reset input Internally connected. (To be directly connected to VDD) Positive power supply GND potential When reset - I/O circuit typeNote -
XT1, XT2
Input
-
-
-
RESET IC VDD VSS
Input -
- -
- -
B
-
- -
- -
- -
- -
Note The circle (
) indicates the Schmitt trigger input.
10
PD75036
3.3 PIN INPUT/OUTPUT CIRCUITS
The input/output circuit of each PD75036 pin is shown below in a simplified manner.
(1/3)
Type A (For type E-B) Type D (For type E-B, F-A) VDD Data P-ch IN Output disable N-ch P-ch OUT
VDD
N-ch
CMOS input buffer Type B
Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch) Type E-B VDD P.U.R. P.U.R. enable P-ch
IN
Data Type D Output disable
IN/OUT
Type A
Schmitt trigger input with hysteresis Type B-C Type E-D
P.U.R.: Pull-Up Resistor
VDD P.U.R. P.U.R. enable
Data Output disable Type D
IN/OUT
P-ch
Type A
P.D.R. enable IN
N-ch
P.D.R.
P.U.R.: Pull-Up Resistor
P.D.R.: Pull-Down Resistor
11
PD75036
(2/3)
Type F-A Type M-C VDD P.U.R. P.U.R. enable P-ch IN/OUT Data Type D Output disable IN/OUT Data Output disable
Type B
VDD P.U.R. P.U.R. enable P-ch
N-ch
P.U.R.: Pull-Up Resistor Type F-B VDD P.U.R. Type Y
P.U.R.: Pull-Up Resistor
AVDD P.U.R. enable Output disable (P) Data Output disable Output disable (N) N-ch AVSS VDD P-ch IN/OUT AVSS Reference voltage (from voltage tap of serial resistor string) Input enable P-ch IN AVDD P-ch N-ch + Sampling C -
P.U.R.: Pull-Up Resistor Type M VDD IN P.U.R. enable (Mask option) IN/OUT Input buffer Data Output disable N-ch (Can sustain +10 V) IN AVDD P-ch N-ch + - Type Y-A
AVDD
Sampling C
AVSS AVSS Middle-voltage input buffer (Can sustain +10 V) P.U.R.: Pull-Up Resistor Reference voltage (from voltage tap of serial resistor string)
12
PD75036
(3/3)
Type Z-A
AVREF+
Reference voltage
AVREF-
3.4
MASK OPTION SELECTION
The following mask options are available for selection for each pin.
Pin name P40 - P43, P50 - P53, P100-P103 XT1, XT2 Mask option
1
Pull-up resistor provided (specifiable bit by bit)
2
Pull-up resistor not provided (specifiable bit by bit)
1
Feedback resistor provided (if a subsystem clock is used)
2
Feedback resistor not provided (if a subsystem clock is not used)
13
PD75036
5 3.5 CONNECTION OF UNUSED PINS
Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P21/PPO P22/PCL P23/BUZ P30-P33 P40-P43 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80-P83 P90-P93 P100/MAR P101/MAI P102/MAZ P103/MAT P110/AN0-P113/AN3 AN4-AN7 AVREF+ AVREFAVSS AVDD XT1 XT2 IC To be connected to VDD To be connected to VSS or VDD To be open To be directly connected to VDD To be connected to VSS To be connected to VSS or VDD : To be connected to VSS or VDD Output state:To be open Input state To be connected to VSS Recommended connection To be connected to VSS To be connected to VSS or VDD
14
PD75036
4. ARCHITECTURE AND MEMORY MAP OF THE PD75036
The PD75036 has two architectural features: * Bank configuration of data memory : Static RAM (1024 words x 4 bits) Peripheral hardware (128 x 4 bits) * Memory mapped I/O Fig. 4-1 and 4-2 show the memory maps for the PD75036.
Address 7 0000H MBE 6 0 5 0 Internal reset start address Internal reset start address 0002H MBE 0 0 INTBT/INT4 start address INTBT/INT4 start address 0004H MBE 0 0 INT0 start address INT0 start address 0006H MBE 0 0 INT1 start address INT1 start address 0008H MBE 0 0 INTCSI start address INTCSI start address 000AH MBE 0 0 INTT0 start address INTT0 start address 000CH MBE 0 0 INTMFT start address INTMFT start address
Fig. 4-1 Program Memory Map
0 (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) CALLF !faddr (low-order 8 bits) instruction (high-order 6 bits) entry address (low-order 8 bits) BR !addr instruction branch address CALL !addr instruction subroutine entry address
BRCB !caddr instruction branch address
BR $addr instruction relative branch address (-15 to -1, +2 to +16)
Branch address and subroutine entry address specified in GETI instruction
0020H GETI instruction reference table 007FH 0080H
07FFH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 1FFFH 2000H BRCB !caddr instruction branch address 2FFFH 3000H BRCB !caddr instruction branch address 3F7FH
Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the low-order 8 bits of the PC changed.
15
PD75036
Fig. 4-2 Data Memory Map
Data memory General register area Stack area 000H (8 x 4) 007H 008H 256 x 4 0FFH 100H
Memory bank
0
256 x 4
1
Data area Static RAM (1024 x 4)
1FFH 200H
256 x 4
2
2FFH 300H
256 x 4
3
3FFH Not contained
F80H Peripheral hardware area FFFH 128 x 4 15
16
PD75036
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS
The PD75036 has the following three types of I/O port: * 12 CMOS input ports (Ports 0, 1, and 11) * 24 CMOS I/O ports (Ports 2, 3, 6, 7, 8, and 9) * 12 N-ch open-drain I/O ports (Ports 4, 5, and 10) Total: 48 ports Table 5-1
Port (symbol) PORT0 PORT1 PORT3Note PORT6 PORT2 PORT7 Allows input or output mode setting in units of four bits. Ports 6 and 7 make a pair, allowing data I/O in units of eight bits. 4-bit I/O (N-ch open-drain, withstand voltage: 10 V) Allows input or output mode setting in units of four bits. Ports 4 and 5 make a pair, allowing data I/O in units of eight bits. Function 4-bit input
Functions of Ports
Remarks Also used as SO/SB0, SI/ SB1, SCK, INT0-INT2, INT4, and TI0 pins. Port 6 is also used as KR0KR3 pins. Port 2 is also used as PTO0, PPO, PCL, and BUZ pins. Also used as KR4-KR7 pins. Use of an internal pull-up registor can be maskprogrammed in units of one bit. Port 10 is also used as MAR, MAI, MAZ, and MAT pins.
Operation and feature Allows input and test at any time regardless of the operation modes of dual function pins.
4-bit I/O
Allows input or output mode setting in units of one bit.
PORT4Note PORT5Note PORT10Note
PORT8 PORT9 PORT11
4-bit I/O
Allows input or output mode setting in units of four bits.
4-bit input
Port for 4-bit input
Port 11 is also used as AN0AN3 pins.
Note Ports 3, 4, 5 and 10 can directly drive an LED. 5.2 CLOCK GENERATOR
Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control register (SCC). The main system clock or subsystem clock can be selected. The instruction execution time is variable. * 0.95 s, 1.91 s, 15.3 s (main system clock: 4.19 MHz) * 122 s (subsystem clock: 32.768 kHz)
17
PD75036
5 Fig. 5-1 Block Diagram of the Clock Generator
XT1 VDD XT2 X1 VDD X2 Main system clock generator fX 1/2 1/16 Subsystem clock generator fXT Clock timer
1/2 to 1/4096 Frequency divider
Multifunction timers Basic interval timer (BT) Timer/event counter Serial interface Clock timer A/D converter (successive approximation) * INT0 noise eliminator * Clock output circuit
* * * * * *
WM.3 SCC SCC3 SCC0
Internal bus
Oscillator disable signal
Selector Frequency divider Selector 1/4 *CPU *INT0 noise eliminator *Clock output circuit
PCC PCC0
PCC1 4 HALTNote STOPNote PCC2 HALT F/F S
PCC3 R Q
PCC2, PCC3 clear signal
STOP F/F Q S
Wait release signal from BT RESET signal
R
Standby release signal from interrupt control circuit
Note Instruction execution Remarks 1. 2. 3. 4. 5. 6. fX : Main system clock frequency fXT : Subsystem clock frequency = CPU clock PCC: Processor clock control register SCC: System clock control register One clock cycle (tCY) of the CPU clock () is equal to one machine cycle of an instruction. See Chapter 10 for details of tCY.
18
PD75036
5.3 CLOCK OUTPUT CIRCUIT The clock output circuit outputs a clock pulse signal on the P22/PCL pin for remote control or for supplying clock pulses to a peripheral LSI device. Fig. 5-2 Configuration of the Clock Output Circuit
From the clock generator f X/2
3
Output buffer Selector PCL/P22
f X/24 f X/2
6
PORT2.2 CLOM3 CLOM2 CLOM1 CLOM0 CLOM P22 output latch
Bit 2 of PMGB
Port 2 input/ output mode specification bit
4 Internal bus
Remark The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output.
19
PD75036
5.4 BASIC INTERVAL TIMER The basic interval timer provides the following functions: * Interval timer operation that generates a reference time interrupt * Application of watchdog timer for detecting program crashes * Selection of a wait time for releasing the standby mode, and counting * Reading the count value Fig. 5-3 Configuration of the Basic Interval Timer
From the clock generator fX/25 fX/2 fX/2 fX/2
7
Clear signal
Clear signal
MPX
9
Basic interval timer (8-bit frequency divider circuit)
Set signal
BT interrupt request flag
12
BT
IRQBT
Vectored interrupt request signal
3
Wait release signal for standby release BTM0 BTM 8 Internal bus
BTM3 SET1Note
BTM2 4
BTM1
Note Instruction execution
20
PD75036
5.5 CLOCK TIMER The PD75036 contains one channel for a clock timer. The clock timer provides the following functions: * The clock timer sets the test flag (IRQW) every 0.5 seconds. The standby mode can be released with IRQW. * Either the main system clock or subsystem clock can produce 0.5-second intervals. * The fast-forward mode produces an interval 128 times faster (3.91 ms), which is useful for program debugging and testing. * An arbitrary frequency (2.048, 4.096, or 32.768 kHz) can be output to the P23/BUZ pin, so that it can be used for sounding the buzzer and system clock frequency trimming. * The frequency divider can be cleared, so the clock can start from zero seconds.
Fig. 5-4
Block Diagram of the Clock Timer
fW 27
(256 Hz: 3.91 ms)
fX From 128 the (32.768 kHz) clock gener fXT ator (32.768 kHz)
fW (32.768 kHz) Selector Frequency divider
4 kHz 2 kHz
fW 214 2 Hz 0.5 sec Clear signal
Selector
INTW IRQW set signal
Selector
Output buffer P23/BUZ
WM WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0
PORT2.3 P23 output latch
Bit 2 of PMGB
Port 2 input/ output mode
8
Bit test instruction
Internal bus
The values in parentheses indicates are for fX = 4.194304 MHz and fXT = 32.768 kHz
21
PD75036
5.6 TIMER/EVENT COUNTER
The PD75036 contains one channel of timer/event counter. The timer/event counter provides the following functions: * Programmable interval timer operation * Output of a square wave at a given frequency to the PTO0 pin * Event counter operation * Frequency divider operation that divides TI0 pin input by N and outputs the result to the PTO0 pin * Supply of serial shift clock signal to a serial interface circuit * Function of reading the state of counting
22
Fig. 5-5
Block Diagram of the Timer/Event Counter
Internal bus 8 SET1
Note
TM0
8
8 TMOD0 Modulo register (8)
TOE0
TO enable flag
PORT2.0
P20 output latch signal
Bit 2 of PGMB
TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00
Port 2 input/ output mode
PORT1.3
8
Match
To serial interface TOUT F/F Reset T0 INTT0 Output buffer P20/PTO0
Comparator (8) 8 Input buffer P13/ TI0 From the clock generator Count register (8) MPX CP Clear signal

IRQT0 set signal
Timer operation start signal RESET IRQT0 clear signal
(See Fig. 5-1.)
Note Instruction execution
PD75036
23
PD75036
5.7 SERIAL INTERFACE
The PD75036 has three modes. * Three-wire serial I/O mode (The first bit is switchable between MSB and LSB.) * Two-wire serial I/O mode (The first bit is MSB.) * SBI mode (The first bit is MSB.) The three-wire serial I/O mode enables connections to be made with the 75X series, 78K series, and many other types of I/O devices. The two-wire serial I/O mode and SBI mode enable communication with two or more devices.
24
Fig. 5-6 Block Diagram of the Serial Interface
Internal bus 8/4 CSIM Bit test 8 8 8 Slave address register (SVA) (8) Match signal Address comparator P03/SI/SB1 SET CLR SO latch Selector Shift register (SIO) (8) D Q (8) RELT CMDT SBIC Bit manipulation Bit test
ACKE
P02/SO/SB0 Selector Bus release/ command/ acknowledge detection circuit P01/SCK RELD CMDD ACKD Busy/ acknowledge output circuit
BSYE
ACKT
INTCSI Serial clock counter INTCSI control circuit IRQCSI set signal fX/23 fX/24 fX/26 TOUT F/F (from timer/event counter) External SCK
P01 output latch
Serial clock control circuit
Serial clock selector
PD75036
25
PD75036
5.8 A/D CONVERTER
The PD75036 contains an 8-bit resolution analog/digital (A/D) converter that has eight analog input channels (AN0 - AN7). The A /D converter employs the successive-approximation method. Fig. 5-7 Configuration of the A/D Converter
Internal bus
8
0
ADM6 ADM5 ADM4
SOC
EOC
0
0
ADM
8
AN0/P110 AN1/P111 AN2/P112
Control circuit Sample and hold circuit +
AN3/P113 AN4 AN5 AN6
Multiplexer
SA register (8)
- Comparator
8 AN7
Tap decoder
AVREF+ R/2 R R Series resistor string R R/2
AVREF--
26
PD75036
5.9 MULTIFUNCTION TIMER (MFT) The PD75036 contains one multifunction timer (MFT). The MFT has four operation modes. Each mode provides the following functions:
* 8-bit timer mode
* Operates as a programmable interval timer. * Outputs a square wave of an arbitrary frequency on the PPO pin.
* PWM output mode
* Outputs a 6-bit, 7-bit, or 8-bit precision PWM signal on the PPO pin.
* 16-bit free-running timer mode
* Operates as an interval timer that generates an interrupt at specified time intervals. * Usable as a one-shot timer.
* Integral A/D converter modes
* Outputs a control signal for a 16-bit integral A/D converter. * Allows a resolution to be selected from 13 bits, 14 bits, 15 bits, and 16 bits.
27
28
Selector MAT/ P103 Edge selector fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Selector MPX 8
Fig. 5-8 Block Diagram of the Multifunction Timer
Internal bus
Clear signal
8
8 Output latch
P21 P100 P101 P102
Input/output mode register MAZ/P102
Count register (MFTL) Modulo latch 8 Match MFT F/F Integral A/D control circuit
MAI/P101 MAR/P100 PPO/P21
Comparator
8 Overflow Count register (MFTH) Tap selector
Interrupt selector
INTMFT IRQMFT set signal
RESET Selector IRQMFT clear signal
MFTM7 MFTM6 MFTM5 MFTM4 MFTM3 MFTM2 MFTM1 MFTM0 MFTM
MFTC3 MFTC2 MFTC1 MFTC0 MFTC 1/4
PD75036
Internal bus
PD75036
6. INTERRUPT FUNCTION
The PD75036 has nine vectored interrupt sources and provides multiple interrupts by software control. It also has two types of edge detected testable input pins. The interrupt control circuitry of the PD75036 has the following features: * Vectored interrupts are controlled by the hardware. Whether to accept an interrupt is controlled by an interrupt flag (IExxx) and interrupt master enable flag (IME). * An interrupt start address can be freely set. * An interrupt request flag (IRQxxx) can be tested. (Whether an interrupt has occurred can be checked by software.) * A standby mode can be released. (What interrupt source to release can be selected using an interrupt enable flag.)
29
30
2 IM2 2 IM1 2 IM0 INT BT INT4/ P00 INT0/ P10 INT1/ P11
Note
Fig. 6-1 Block Diagram of Interrupt Control Circuit
Internal bus
IME Interrupt enable flag (IExxx)
IST0
IRQBT VRQn
Decoder
Both-edge detection circuit Edge detection circuit Edge detection circuit INTCSI
IRQ4
IRQ0
IRQ1 Vector table address generator
IRQCSI
Priority control circuit
INTT0
IRQT0
INTMFT
IRQMFT
INTW INT2/ P12 Rising edge detection circuit Falling edge detection circuit
IRQW
Selector
IRQ2
Standby release signal
KR0/P60 KR7/P73
PD75036
IM2
Note Noise eliminator
PD75036
7. STANDBY FUNCTION
To reduce the power consumption of the system waiting for a program input, the PD75036 has two standby modes STOP and HALT modes. Table 7-1 Standby Modes and Operation Status
STOP mode Instruction for setting System clock at setting STOP instruction This mode can be set only when the main system clock is used. HALT mode HALT instruction This mode can be set when either the main system clock or subsystem clock is used. Only CPU clock is stopped (with oscillation continued). Operation is possible only when the main system clock is oscillated. (Sets IRQBT at reference time intervals) Operation is possible only when external SCK input is selected for the serial clock or the main system clock is oscillated. Operation is possible only when TI0 pin input is selected for the count count clock or the main system clock is oscillated. Operation is possible. Operation is possible.Note Operation is possible.Note
Clock generator
Only the main system clock is stopped.
Basic interval timer
Operation is stopped.
Serial interface Operation status
Operation is possible only when external SCK input is selected for the serial clock.
Timer/event counter
Operation is possible only when TI0 pin input is selected for the count clock.
Clock timer
Operation is possible when fXT is selected for the count clock. Operation is stopped. Operation is stopped.
A/D converter Multifunction timer External interrupt CPU Release signal
INT1, INT2, and INT4 are enabled. INT0 is disabled. Operation is stopped. Interrupt request signals sent out from hardware, which are enabled by interrupt enable flags, or RESET input Interrupt request signals sent out from hardware, which are enabled by interrupt enable flags, or RESET input
Note Operation is possible only when the main system clock operates.
8. RESET FUNCTION
The PD75036 is reset by RESET signal input.
31
PD75036
9. INSTRUCTION SET
(1) Operand identifier and its descriptive method The operands are described in the operand column of each instruction according to the descriptive method for the operand format of the appropriate instructions (refer to RA75X Assembler Package User's Manual,
Language (EEU-1363) for details). For descriptions in which alternatives exist, one element should be
selected. Capital letters and plus and minus signs are keywords; therefore, they should be described as they are. For immediate data, the appropriate numerical values or labels should be described.
Identifier reg reg1 rp rp1 rp2 rpa rpa1 n4 n8 memNote bit fmem pmem addr caddr faddr taddr PORTn IExxx MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE HL, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label FB0H - FBFH, FF0H - FFFH immediate data or label FC0H - FFFH immediate data or label 0000H - 3F7FH immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20H - 7FH immediate data (however, bit 0 = 0) or label PORT0 - PORT11 IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW, IEMFT MB0, MB1, MB2, MB3, MB15 Description
Note Only even address can be specified for mem when processing 8-bit data. (2) Symbol definitions in operation description A B C D E H L : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register
32
PD75036
X XA BC DE HL PC SP CY PSW MBE IME IExxx MBS PCC . (xx) xxH : X register : Pair register (XA); 8-bit accumulator : Pair register (BC) : Pair register (DE) : Pair register (HL) : Program counter : Stack pointer : Carry flag; Bit accumulator : Program status word : Memory bank enable flag : Interrupt master enable flag : Interrupt enable flag : Memory bank selection register : Processor clock control register : Address bit delimiter : Contents addressed by xx : Hexadecimal data
PORTn : Port n (n = 0 to 11)
(3) Explanation of the symbols in the addressing area field
*1 MB = MBE*MBS (MBS = 0, 1, 2, 3, or 15) MB = 0 MBE = 0: MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1: MB = MBS (MBS = 0, 1, 2, 3, or 15) MB = 15, fmem = FB0H-FBFH or FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr = 0000H-3F7FH addr = (Current PC) - 15 to (Current PC) - 1 or (Current PC) + 2 to (Current PC) + 16 caddr = 0000H-0FFFH (PC13,12 = 00B) or 1000H-1FFFH (PC13,12 = 01B) or 2000H-2FFFH (PC13,12 = 10B) or 3000H-3F7FH (PC13,12 = 11B) faddr = 0000H-07FFH taddr = 0020H-007FH Program memory addressing Data memory addressing
*2 *3
*4
*5 *6 *7
*8
*9 *10
Remarks 1. MB indicates an accessible memory bank. 2. For *2, MB is always 0 irrespective of MBE and MBS. 3. For *4 and *5, MB is always 15 irrespective of MBE and MBS. 4. *6 to *10 indicate each addressable area.
33
PD75036
(4) Description of machine cycle column S indicates the number of machine cycles necessary for skipping any skip instruction. The value of S changes as follows: * When no skip is performed******************************************************************************************************************* * When a 1-byte or 2-byte instruction is skipped *********************************************************************************** * When a 3-byte instruction (BR !addr, CALL !addr instruction) is skipped ***************************************** Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equivalent to one CPU clock cycle (tCY). Therefore, the length of the machine cycle can be selected from three different lengths by the PCC setting. S=0 S=1 S=2
34
PD75036
MachinBytes ing cycle 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 1 1 1 1 1 1 1 2 1 2 1 2 1 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 3 3 1+S 1+S 1 1+S 1 2 1 2 1 2 1 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg1 XA rp reg1 A rp1 XA A (HL) A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp XA (PC13-8 + DE)ROM XA (PC13-8 + XA)ROM A A + n4 A A + (HL) A, CY A + (HL) + CY A A - (HL) A, CY A - (HL) - CY *1 *1 *1 *1 borrow carry carry *1 *2 *1 *3 *3 *1 *2 *1 *1 *1 *3 *3 *3 *3 String A String B
Group
Mnemonic MOV
Operand
Operation
Addressing area
Skip condition String A
Transfer
A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg1 XA, rp reg1, A rp1, XA
XCH
A, @HL A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp
Table reference Arithmetic
MOVT
XA, @PCDE XA, @PCXA
ADDS
A, #n4 A, @HL
ADDC SUBS SUBC AND
A, @HL A, @HL A, @HL A, #n4 A, @HL
OR
A, #n4 A, @HL
XOR
A, #n4 A, @HL
n4 A A (HL) A A n4 A A (HL) A A n4 A A (HL)
AA
*1
*1
*1
35
PD75036
MachinBytes ing cycle 1 2 1 2 2 1 2 2 1 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 1+S 2+S 2+S 1+S 2+S 2+S 1+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2
Group
Accumulator manipulation
Mnemonic RORC NOT INCS A A reg
Operand
Operation CY A0, A3 CY, An-1 An AA reg reg + 1 (HL) (HL) + 1 (mem) (mem) + 1 reg reg - 1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if A = reg CY 1 CY 0 Skip if CY = 1 CY CY (mem.bit) 1 (fmem.bit) 1 (pmem7-2 + L3-2.bit(L1-0)) 1 (H + mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2 + L3-2.bit(L1-0)) 0 (H + mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 Skip if (H + mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2 + L3-2.bit(L1-0)) = 0 Skip if (H + mem3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 and clear Skip if (H + mem3-0.bit) = 1 and clear
Addressing area
Skip condition
Increment/ decrement
reg = 0 *1 *3 (HL) = 0 (mem) = 0 reg = FH reg = n4 *1 *1 (HL) = n4 A = (HL) A = reg
@HL mem DECS reg reg, #n4 @HL, #n4 A, @HL A, reg
Comparison
SKE
Carry flag manipulation
SET1 CLR1 SKT NOT1
CY CY CY CY mem.bit fmem.bit pmem. @L @H+mem.bit
CY = 1
Memory bit manipulation
SET1
*3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1
(@H + mem.bit) = 1
CLR1
mem.bit fmem.bit pmem. @L @H+mem.bit
SKT
mem.bit fmem.bit pmem. @L @H+mem.bit
SKF
mem.bit fmem.bit pmem. @L @H+mem.bit
(mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0
(@H + mem.bit) = 0
SKTCLR
fmem.bit pmem. @L @H+mem.bit
(fmem.bit) = 1 (pmem.@L) = 1
(@H + mem.bit) = 1
AND1
CY, fmem.bit CY, pmem. @L CY, @H+mem.bit
OR1
CY, fmem.bit CY, pmem. @L CY, @H+mem.bit
(fmem.bit) CY CY (pmem7-2 + L3-2.bit(L1-0)) CY CY (H + mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit(L1-0)) CY CY (H + mem3-0.bit)
CY CY
36
PD75036
MachinBytes ing cycle 2 2 2 - 2 2 2 - CY CY
Group
Mnemonic XOR1
Operand
Operation
Addressing area *4 *5 *1 *6
Skip condition
Memory bit manipulation Branch
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
(fmem.bit) CY CY (pmem7-2 + L3-2.bit(L1-0)) CY CY (H + mem3-0.bit)
PC13-0 addr (Appropriate instructions are selected from BR !addr, BRCB !caddr, and BR $addr by the assembler.) PC13-0 addr PC13-0 addr PC13-0 PC13, 12 + caddr11-0 (SP - 4)(SP - 1)(SP - 2) PC11-0 (SP - 3) MBE, 0, PC13, PC12 PC13-0 addr, SP SP - 4 (SP - 4)(SP - 1)(SP - 2) PC11-0 (SP-3) MBE, 0, PC13, PC12 PC13-0 000, faddr, SP SP - 4
BR
addr
!addr $addr BRCB Subroutine stack control CALL !caddr !addr
3 1 2 3
3 2 2 3
*6 *7 *8 *6
CALLF
!faddr
2
2
*9
RET
1
3
MBE, 0, PC13, PC12 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) SP SP + 4 MBE, 0, PC13, PC12 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) SP SP + 4, then skip unconditionally MBE, 0, PC13, PC12 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) PSW (SP + 4)(SP + 5), SP SP + 6 (SP - 1)(SP - 2) rp, SP SP - 2 (SP - 1) MBS, (SP - 2) 0, SP SP - 2 rp (SP + 1)(SP), SP SP + 2 MBS (SP + 1), SP SP + 2 IME 1 IExxx 1 IME 0 IExxx 0 A PORTn (n = 0 - 11) Unconditional
RETS
1
3+S
RETI
1
3
PUSH
rp BS
1 2 1 2 2
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1
POP
rp BS
Interrupt control
EI IExxx DI IExxx
2 2 2 2 2 2 2 2 2 1
Input/ output
INNote
A, PORTn XA, PORTn
XA PORTn+1,PORTn (n = 4, 6) PORTn A (n = 2 - 10)
OUTNote
PORTn, A PORTn, XA
PORTn+1,PORTn XA (n = 4, 6) Set HALT Mode Set STOP Mode No Operation (PCC.2 1) (PCC.3 1)
CPU control
HALT STOP NOP
37
PD75036
MachinBytes ing cycle 2 1 2 3
Group
Mnemonic SEL GETI
Operand
Operation MBS n (n = 0, 1, 2, 3, or 15) * For the TBR instruction PC13-0 (taddr)5-0 + (taddr + 1)
Addressing area
Skip condition
Special
MBn taddr
*10
---------------------------------------------* For the TCALL instruction (SP - 4)(SP - 1)(SP - 2) PC11-0 (SP - 3) MBE, 0, PC13, PC12 PC13-0 (taddr)5-0 + (taddr + 1) SP SP - 4 For other than the TBR and TCALL instruction (taddr) (taddr + 1) is executed.
-----------------
---------------------------------------------*
----------------Depends on the reference instruction
Caution When executing the IN/OUT instruction, MBE must be set to 0 or MBE and MBS must be set to 1 and 15, respectively.
38
PD75036
10. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Ports other than ports 4, 5, and 10 Ports 4, 5, Built-in pull-up resistor and 10 Open drain Conditions Rated value -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +11 -0.3 to VDD + 0.3 1 pin All pins IOLNote 1 pin of parts 0, 3, 4, and 5 Peak value rms 1 pin of ports other than ports 0, 3, 4 and 5 Total of all pins of ports 3 to 9 and 11 Total of all pins of ports 0, 2, and 10 Operating temperature Storage temperature Topt Peak value rms Peak value rms Peak value rms -10 -30 30 15 20 5 170 120 30 20 -40 to +85 Unit V V V V V mA mA mA mA mA mA mA mA mA mA C 5
Output voltage High-level output current Low-level output current
VO IOH
Tstg
-65 to +150
C
Note Calculate rms with [rms] = [peak value] x duty.
39
PD75036
CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Resonator Ceramic resonator
C1
Recommended constant
X1 X2 VDD
Parameter Oscillator frequency (fX) Note 1 Oscillation settling time
Note 2
Conditions
Min. 1.0
Typ.
Max. 5.0
Unit MHz
C2
4
ms
VDD
Crystal resonator
C1
X1
X2 VDD
Oscillator frequency (fX) Note 1 Oscillation settling time
Note 2
1.0
4.19
5.0Note 3
MHz
C2
VDD = 4.5 to 6.0 V
10 30 1.0 5.0
ms ms MHz
VDD
External clock
X1
X2
X1 input frequency (fX) Note 1
X1 input PD74HCU04 high/low level width (tXH, tXL)
100
500
ns
Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. 2. The oscillation settling time means the time required for the oscillation to settle after VDD is applied or after the STOP mode is released. 3. When 4.19 MHz < fX 5.0 MHz, do not select PCC = 0011 as the instruction execution time. When PCC = 0011, one machine cycle falls short of 0.95 s, the minimum value for the standard. Caution When the main system clock oscillator is used, conform to the following guidelines when wiring at the portions of surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. * The wiring must be as short as possible. * Other signal lines must not run in these areas. * Any line carrying a high fluctuating current must be kept away as far as possible. * The grounding point of the capacitor of the oscillator must have the same potential as that of VDD. It must not be grounded to ground patterns carrying a large current. * No signal must be taken from the oscillator.
40
PD75036
CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Resonator Crystal resonator Recommended constant
XT1 XT2 VDD R
C3 C4
Parameter Oscillator frequency (fXT) Note 1 Oscillation settling time
Note 2
Conditions
Min. 32
Typ. 32.768
Max. 35
Unit kHz
VDD = 4.5 to 6.0 V
1.0
2 10
s s kHz
VDD
External clock
XT1
XT2
XT1 input frequency (fXT) Note 1 XT1 input high/low level width (tXTH, tXTL)
32
100
5
15
s
Notes 1. 2.
The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. The oscillation settling time means the time required for the oscillation to settle after VDD reaches Min. of the oscillation voltage range.
Caution When the subsystem clock oscillator is used, conform to the following guidelines when wiring at the portions of surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. * The wiring must be as short as possible. * Other signal lines must not run in these areas. * Any line carrying a high fluctuating current must be kept away as far as possible. * The grounding point of the capacitor of the oscillator must have the same potential as that of VDD. It must not be grounded to ground patterns carrying a large current. * No signal must be taken from the oscillator. When the subsystem clock is used, pay special attention to its wiring; the subsystem clock oscillator has low amplification to minimize current consumption and is more likely to malfunction due to noise than the main system clock oscillator. CAPACITANCE (Ta = 25 C, VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Conditions f = 1 MHz 0 V for pins other than pins to be measured Min. Typ. Max. 15 15 15 Unit pF pF pF
41
PD75036
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter High-level input voltage
Symbol VIH1 VIH2 VIH3
Conditions Ports 2, 3, 8, 9, and 11 Ports 0, 1, 6, and 7 and RESET Ports 4, 5, Built-in pull-up resistor and 10 Open drain X1, X2, XT1, and XT2 Ports 2 to 5 and 8 to 11 Ports 0, 1, 6, and 7 and RESET X1, X2, XT1, and XT2 VDD = 4.5 to 6.0 V, IOH = -1 mA IOH = -100 A
Min. 0.7VDD 0.8VDD 0.7VDD 0.7VDD VDD - 0.5 0 0 0 VDD - 1.0 VDD - 0.5
Typ.
Max. VDD VDD VDD 10 VDD 0.3VDD 0.2VDD 0.4
Unit V V V V V V V V V V
VIH4 Low-level input voltage VIL1 VIL2 VIL3 High-level output voltage Low-level output voltage VOH
VOL
Ports 3, 4, VDD = 4.5 to 6.0 V, IOL = 15 mA and 5 VDD = 4.5 to 6.0 V, IOL = 1.6 mA IOL = 400 A SB0 and SB1 Open drain Pull-up resistor: 1 k or more Other than X1, X2, XT1, and XT2 X1, X2, XT1, and XT2 VI = 10 V VI = 0 V Ports 4, 5, and 10 (open drain) Other than X1, X2, XT1, and XT2 X1, X2, XT1, and XT2 VO = VDD Other than ports 4, 5, and 10
0.5
2.0
V
0.4 0.5 0.2VDD
V V V
High-level input leakage current
ILIH1 ILIH2 ILIH3
VI = VDD
3 20 20 -3 -20 3 20 -3
A A A A A A A A
k k k k k k
Low-level input leakage current High-level output leakage current Low-level output leakage current Built-in pull-up resistor
ILIL1 ILIL2 ILOH1 ILOH2 ILOL
VO = 10 V Ports 4, 5, and 10 (open drain) VO = 0 V VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 %
RU1
Ports 0, 1, 2, 3, 6, 7, and 8 (excl. P00) VI = 0 V Ports 4, 5, and 10 VO = VDD - 2.0 V Port 9 VI = VDD
15 30 15 10 10 10
40
80 300
RU2
40
70 60
Built-in pull-down resistor
RD
40
70 60
42
PD75036
Parameter Power supply currentNote 1 Symbol IDD1 4.19 crystal resonance C1 = C2 = 22 pF MHzNote 2 Conditions VDD = 5 V 10 VDD = 3 V 10 HALT mode %Note 3 %Note 4 VDD = 5 V 10 % VDD = 3 V 10 % VDD = 3 V 10 % VDD = 3 V 10 % VDD = 5 V 10 % VDD = 3 V 10 % Ta = 25 C Min. Typ. 3.2 0.25 500 150 15 5 0.5 0.1 0.1 Max. 10 0.75 1500 450 45 15 20 10 5 Unit mA mA
IDD2
A A A A A A A
IDD3 IDD4 IDD5
32.768 kHzNote 5 crystal HALT mode resonance XT1 = 0 V STOP mode
Notes 1. 2. 3. 4. 5.
This current excludes the current which flows through the built-in pull-up resistors. This value applies also when the subsystem clock oscillates. Value when the processor clock control register (PCC) is set to 0011 and the PD75036 is operated in the high-speed mode Value when the PCC is set to 0000 and the PD75036 is operated in the low-speed mode This value applies when the system clock control register (SCC) is set to 1001 to stop the main system clock pulse and to start the subsystem clock pulse.
43
PD75036
AC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.0 to 6.0 V)
Parameter CPU clock cycle time (minimum instruction execution time = 1 machine cycle)Note 1
Symbol tCY
Conditions Operated by main system clock pulse Operated by subsystem clock pulse VDD = 4.5 to 6.0 V
Min. 0.95 3.8 114
Typ.
Max. 64 64
Unit
s s s
122
125
TI0 input frequency
fTI
VDD = 4.5 to 6.0 V
0 0
1 275
MHz kHz
TI0 input high/low level width Interrupt input high/low level width
tTIH, tTIL tINTH, tINTL
VDD = 4.5 to 6.0 V
0.48 1.8
s s s s s s
INT0 INT1, INT2, and INT4 KR0 to KR7
Note 2
10 10 10
RESET low level width
tRSL
Notes 1. The cycle time of the CPU clock () depends on the connected resonator frequency, the system clock control register (SCC), and the processor clock control register (PCC). The figure on the right side shows the cycle time tCY characteristics for the supply voltage VDD during main system clock
Cycle time tCY [ s]
tCY vs VDD
(Main system clock in operation) 70 64 60 6 5 4 3 Operation guaranteed range
operation. 2. This value becomes 2tCY or 128/fX according to the setting of the interrupt mode register (IM0).
2
1
0.5 0 1 2 3 4 5 6
Power supply voltage VDD [V]
44
PD75036
Serial transfer operation Two-wire and three-wire serial I/O modes (SCK ... Internal clock output):
Max.
Parameter SCK cycle time
Symbol tKCY1
Conditions VDD = 4.5 to 6.0 V
Min. 1600 3800
Typ.
Unit ns ns ns ns ns
SCK high/low level width SI setup time (referred to SCK) SI hold time (referred to SCK) Delay time from SCK to SO output
tKL1 tKH1 tSIK1
VDD = 4.5 to 6.0 V
tKCY1/2 - 50 tKCY1/2 - 150 150
tKSI1
400
ns
tKSO1
RL = 1 k, CL = 100 pFNote
VDD = 4.5 to 6.0 V
0 0
250 1000
ns ns
Two-wire and three-wire serial I/O modes (SCK ... External clock input):
Parameter SCK cycle time
Symbol tKCY2
Conditions VDD = 4.5 to 6.0 V
Min. 800 3200
Typ.
Max.
Unit ns ns ns ns ns
SCK high/low level width SI setup time (referred to SCK) SI hold time (referred to SCK) Delay time from SCK to SO output
tKL2 tKH2 tSIK2
VDD = 4.5 to 6.0 V
400 1600 100
tKSI2
400
ns
tKSO2
RL = 1 k, CL = 100 pFNote
VDD = 4.5 to 6.0 V
0 0
300 1000
ns ns
Note RL and CL are the resistance and capacitance of the SO output line load respectively.
45
PD75036
SBI mode (SCK ... Internal clock output (master)):
Parameter SCK cycle time Symbol tKCY3 Conditions VDD = 4.5 to 6.0 V Min. 1600 3800 SCK high/low level width SB0/SB1 setup time (referred to SCK) SB0/SB1 hold time (referred to SCK) Delay time from SCK to SB0/SB1 output From SCK to SB0/SB1 From SB0/SB1 to SCK SB0/SB1 low level width SB0/SB1 high level width tKL3 tKH3 tSIK3 VDD = 4.5 to 6.0 V tKCY3/2 - 50 tKCY3/2 - 150 150 Typ. Max. Unit ns ns ns ns ns
tKSI3
tKCY3/2
ns
tKSO3
RL = 1 k, CL = 100 pFNote
VDD = 4.5 to 6.0 V
0 0 tKCY3 tKCY3 tKCY3 tKCY3
250 1000
ns ns ns ns ns ns
tKSB tSBK tSBL tSBH
SBI mode (SCK ... External clock input (slave)):
Parameter SCK cycle time Symbol tKCY4 Conditions VDD = 4.5 to 6.0 V Min. 800 3200 SCK high/low level width SB0/SB1 setup time (referred to SCK) SB0/SB1 hold time (referred to SCK) Delay time from SCK to SB0/SB1 output From SCK to SB0/SB1 From SB0/SB1 to SCK SB0/SB1 low level width SB0/SB1 high level width tKL4 tKH4 tSIK4 VDD = 4.5 to 6.0 V 400 1600 100 Typ. Max. Unit ns ns ns ns ns
tKSI4
tKCY4/2 300 1000
ns
tKSO4
RL = 1 k, CL = 100 pFNote
VDD = 4.5 to 6.0 V
0 0 tKCY4 tKCY4
ns ns ns ns
tKSB tSBK
tSBL tSBH
tKCY4 tKCY4
ns ns
Note RL and CL are the resistance and capacitance of the SB0/SB1 output line load respectively.
46
PD75036
A/D converter (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V)
Parameter Resolution Absolute accuracyNote 1 2.5 V AVREF VDD -10 Ta +85C -40 Ta < -10C Conversion timeNote 2 Sampling timeNote 3 Analog input voltage Analog power supply voltage Reference input voltageNote4 Reference output voltageNote 4 Analog input impedance AVREF current tCONV tSAMP VIAN AVDD 2.5 V (AVREF +) - (AVREF -) 2.5 V (AVREF +) - (AVREF -) AVREF2.5 Symbol Conditions Min. 8 Typ. 8 Max. 8 1.5 2.0 168/fX 44/fX AVREF+ VDD Unit bit LSB
s s
V V
AVREF+
2.5
AVDD
V
AVREF-
0
1.0
V
RAN
1000
M
AIREF
1.0
2.0
mA
Notes 1. Absolute accuracy excluding quantization error (1/2 LSB) 2. Time from the execution of a conversion start instruction till the end of conversion (EOC = 1) (40.1 s: fX = 4.19 MHz) 3. Time from the execution of a conversion start instruction till the end of sampling (10.5 s: fX = 4.19 MHz) 4. The value resulting from subtracting (AVREF-) from (AVREF+) must be greater than or equal to 2.5 V.
47
PD75036
AC Timing Measurement Points (Excluding (X1 and XT1 Inputs)
0.8VDD 0.2VDD
Measurement point
0.8VDD 0.2VDD
Clock Timing
1/fX tXL tXH
VDD - 0.5 V X1 input 0.4 V
1/fXT tXTL tXTH
VDD - 0.5 V XT1 input 0.4 V
TI0 Timing
1/fTI tTIL tTIH
TI0
48
PD75036
Serial Transfer Timing Three-wire serial I/O mode:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI
Input data
tKSO1
SO
Output data
Two-wire serial I/O mode:
tKCY2 tKL2 tKH2
SCK
tSIK2
tKSI2
SB0 and SB1
tKSO2
49
PD75036
Serial Transfer Timing Bus release signal transfer:
tKCY3 tKCY4 tKL3 tKL4 SCK tSIK3 tSIK4 tKSI3 tKSI4 tKH3 tKH4
tKSB
tSBL
tSBH
tSBK
SB0 and SB1 tKSO3 tKSO4
Command signal transfer:
tKCY3 tKCY4 tKL3 tKL4 SCK tSIK3 tSIK4 tKSI3 tKSI4 tKH3 tKH4
tKSB
tSBK
SB0 and SB1 tKSO3 tKSO4
Interrupt Input Timing
tINTL INT0, INT1, INT2 and INT4 KR0-KR7
tINTH
RESET Input Timing
tRSL
RESET
50
PD75036
DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE (Ta = -40 to +85 C)
Parameter Data hold supply voltage Data hold supply currentNote 1 Release signal setting time Oscillation settling timeNote 2 Symbol VDDDR IDDDR tSREL tWAIT Release by RESET Release by interrupt request VDDDR = 2.0 V 0 217/fX
Note 3
Conditions
Min. 2.0
Typ.
Max. 6.0
Unit V
0.1
10
A s
ms ms
Notes 1. 2. 3.
Excluding the current which flows through the built-in pull-up resistors CPU operation stop time for preventing unstable operation at the beginning of oscillation This value depends on the settings of the basic interval timer mode register (BTM) shown below.
Wait time (Values at fx = 4.19 MHz in parentheses) 220/fX (approx. 250 ms) 217/fX (approx. 31.3 ms) 215/fX (approx. 7.82 ms) 213/fX (approx. 1.95 ms)
BTM3 -- -- -- --
BTM2 0 0 1 1
BTM1 0 1 0 1
BTM0 0 1 1 1
Data Hold Timing (STOP Mode Release by RESET)
Internal reset operation HALT mode STOP mode Data hold mode Operation mode
VDD
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
Data Hold Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode STOP mode Data hold mode Operation mode
VDD
VDDDR STOP instruction execution
tSREL
Standby release signal (Interrupt request)
tWAIT
51
PD75036
11. PACKAGE DIMENSIONS
64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K L
J I
F D
G
H
N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS A B C D F G H I J K L M N R 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010+0.004 -0.003 0.007 0~15 P64C-70-750A,C-1
52
PD75036
64 PIN PLASTIC QFP (
14)
A B
48 49
33 32 detail of lead end
C
D
S
64 1
17 16
F
G
H
IM
J
K
P
N
L P64GC-80-AB8-3 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.55 0.1 0.1 2.85 MAX. INCHES 0.693 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
M
55
Q
53
PD75036
5 APPENDIX A DEVELOPMENT TOOLS
The following development tools are provided for developing systems including the PD75036:
IE-75000-RNote 1 IE-75001-R IE-75000-R-EMNote 2 Hardware EP-75028CW-R EP-75028GC-R
In-circuit emulator for the 75X series
Emulation board for the IE-75000-R and IE-75001-R Emulation probe for the PD75036CW
Emulation probe for the PD75036GC. A 64-pin conversion socket, the EV-9200GC-64, is EV-9200GC-64 attached to the probe. PROM programmer PROM programmer adapter for the PD75P036CW. Connected to the PG-1500. PROM programmer adapter for the PD75P036GC. Connected to the PG-1500. Host machine * PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00ANote 3) * IBM PC/AT TM series (PC DOSTM Ver. 3.10)
PG-1500 PA-75P036CW PA-75P036GC IE control program Software PG-1500 controller RA75X relocatable assembler
Notes 1. Maintenance service only 2. Not contained in the IE-75001-R 3. These software cannot use the task swap function, which is available in MS-DOS Ver. 5.00 and Ver. 5.00A.
54
PD75036
APPENDIX B RELATED DOCUMENTS
Documents related to the device
Document Name User's manual Application note 75X series selection guide Document No. IEU-1294 IEM-1294 IF-1027
5
Documents related to development tools
Document Name IE-75000-R User's Manual IE-75001-R User's Manual Hardware IE-75000-R-EM User's Manual EP-75028CW-R User's Manual EP-75028GC-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual Operation Language PG-1500 Controller User's Manual Document No. EEU-1297 EEU-1416 EEU-1294 EEU-1314 EEU-1306 EEU-1335 EEU-1346 EEU-1363 EEU-1291
Other documents
Document Name PACKAGE MANUAL SMD SURFACE MOUNT TECHNOLOGY MANUAL QUALITY GRADES ON NEC SEMICONDUCTOR DEVICES NEC SEMICONDUCTOR DEVICE RELIABILITY/QUALITY CONTROL SYSTEM ELECTROSTATIC DISCHARGE (ESD) TEST GUIDE TO QUALITY ASSURANCE FOR SEMICONDUCTOR DEVICES Document No. IEI-1213 IEI-1207 IEI-1209 IEI-1203 IEI-1201 MEI-1202
Caution The above documents may be revised without notice. Use the latest versions when you design an application system.
55
PD75036
[MEMO]
56
PD75036
Cautions on CMOS Devices
1
Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way. CMOS-specific handling of unused input pins Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediatelevel input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the VDD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document. Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first.
2
3
57
PD75036
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation.
68

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